EGC208 ------------------------------- VHDL Lab ------------------------------- Dr. Izadi

1. Go through the VHDL Tutorial and the tutorial on Xilinix VHDL.

2. Using VDHL, design of a 4-bit ALU that performs the following operations. In addition, your circuit should generate N (sign), Z (zero), C (carry), O (overflow) status signals. Make sure your design only has a single carry line between stages.

3. Simulate it using ModelSim and download and test it on the FPGA board.

** For additional tutorial on VHDL see 4-bit adder.

Arithmetic Operations:	Logical Operations:
Add: A + B	AND: A B
Subtract: A - B	OR: A + B
Increment: A+1	XOR A XOR B
Decrement: A - 1	NOT: A'

Verify the circuit and have it signed by your instructor or TA.

For more detailed tutorial on VHDL visit http://esd.cs.ucr.edu/labs/tutorial/